Peak-to-peak voltage detection circuits receive an input signal voltage (V.sub.IN) and produce an output voltage (V.sub.OUT) which is proportional to the peak-to-peak magnitude of an alternating current (AC) component of the input signal voltage. For example, if such a circuit were to receive as an input signal voltage a sinusoidal signal with a 3 volt peak-to-peak (AC) amplitude superimposed upon a 2 volt direct current (DC) voltage, the peak-to-peak detection circuit would produce an output voltage proportional to the 3 volt peak-to-peak amplitude of the sinusoidal (AC) component of the input signal. (Ideally, a peak-to-peak voltage detector is insensitive to any DC component of the input signal voltage.) If the amplitude of the sinusoidal component of the input signal voltage were reduced to 1.5 Volts peak-to-peak (Vpp), the output voltage of the peak-to-peak voltage detector would be reduced by half (relative to the output voltage produced for the 3 Vpp sinusoid). If the exemplary 2 Volt DC component of the input signal were gradually reduced to zero volts, the output of the peak-to-peak voltage detector would, ideally, be substantially unaffected.
FIG. 1 is a schematic diagram of a prior-art peak-to-peak voltage detector 100 such as may be found in many electrical engineering textbooks. The peak-to-peak voltage detector 100 has two principal portions (circuits): a clamp portion 102 and a peak-detector portion 104. An input signal voltage V.sub.IN is AC-coupled via an input capacitor 110 to the clamp portion 102 of the peak-to-peak voltage detector 100. The clamp portion 102 is implemented by the input capacitor 110, a resistor 120 and a diode 130, all having a common terminal at a voltage V.sub.J at their junction. The voltage V.sub.J is prevented from falling more than one "diode drop" below zero volts (i.e., more than the forward conducting voltage of the diode 130 below ground, or zero volt, level) which effectively causes the voltage V.sub.J at the junction of the capacitor 110, the resistor 120 and the diode 130 to equal the AC component of the input signal voltage V.sub.IN, biased such that the DC level of the negative-most excursions of the AC component are set approximately one diode drop below zero volts. This is known as "clamping" the input voltage to one diode drop below zero volts.
In the peak-detector portion 104 of the peak-to-peak voltage detector 100, the "clamped" junction voltage V.sub.J is applied, via a diode 140, to an RC circuit having a "hold" capacitor 150 and a resistor 160. When the "clamped" junction voltage V.sub.J rises more than one diode drop above a voltage on the "hold" capacitor 150, the diode 140 conducts, permitting current to flow, and the voltage (V.sub.OUT) on the hold capacitor rises until the clamped junction voltage falls below one diode drop above V.sub.OUT. The resistor 160 continually bleeds current away from the capacitor 150, causing V.sub.OUT to fall slowly towards 0 volts so that decreasing peak-to-peak signal amplitude at the input V.sub.IN will cause a corresponding decrease in the output voltage V.sub.OUT. The values of the hold capacitor 150 and the resistor 160 are chosen such that the rate of decay of the voltage V.sub.OUT is very slow compared to the rate of change of the input voltage V.sub.IN. Effectively, then, the output of the peak detect portion 104 of the peak-to-peak detector 100 rises rapidly to a peak level, then decays slowly away from that level.
In order for such a peak-to-peak voltage detector to function properly, the impedance of the input capacitor 110 must be substantially smaller than the resistance of the resistor 120 at the lowest AC frequencies of interest in the input signal voltage. That is, where f.sub.L is the lowest frequency of interest in the input signal voltage V.sub.IN : EQU 1/(2.pi.f.sub.L C.sub.IN)&lt;&lt;R.sub.IN
where C.sub.IN is the capacitance value of the input capacitor 110 and R.sub.IN is the resistance value of the resistor 120. Further, the hold capacitor 150 must be smaller in value than the input capacitor 110, so that following inequality is satisfied: EQU 1/(2.pi.R.sub.HOLD C.sub.HOLD)&lt;&lt;f.sub.L
Although simple in concept, the peak-to-peak voltage detector 100 is subject to many sources of error. The voltage drops across the two diodes 130 and 140 appear as a negative DC shift in the output voltage (voltage on the hold capacitor 150) V.sub.OUT. Further, the circuit will not function properly for AC input signal components less than the sum of the two diode (130, 140) drops. The diodes 130 and 140 have junction capacitances and series resistances which contribute to error. As a result, the peak-to-peak voltage detector 100 is not very accurate, and is best suited only to input signals having relatively large magnitudes (i.e. several volts AC peak-to-peak).
Because of the diodes used, numerous error sources, and the nature and relative sizes of the components required, and because the circuit lacks suitability to small-signal applications, the peak-to-peak detector 100 is not well suited to application in Complementary Metal-Oxide-Silicon (CMOS) integrated circuits.
FIG. 2 is a block diagram of another prior-art peak-to-peak voltage detector 200 which is considerably more accurate, but considerably more complicated than the peak-to-peak detector 100 of FIG. 1. An input buffer amplifier 210 buffers an input signal voltage V.sub.IN and passes it to two separate peak voltage detectors: a positive peak detector 220 and a negative peak detector 230. The positive peak detector 220 detects and holds the value of the positive peak excursions of the input signal voltage V.sub.IN at an output thereof. The negative peak detector 230 detects and holds the value of the negative peak excursions of the input signal voltage V.sub.IN at an output thereof. If there is a DC (or very low frequency component) to the input signal voltage V.sub.IN, it will be present in equal amounts at the outputs of the positive and negative peak detectors 220 and 230. A summing block 240 is used to subtract the output of the negative peak detector 230 from the output of the positive peak detector 220, yielding an output V.sub.OUT equal to the voltage difference between the positive peak excursions and negative peak excursions of the input signal voltage V.sub.IN --in other words, V.sub.OUT equals the peak-to-peak value of the input signal voltage V.sub.IN.
Although considerably more accurate than the peak-to-peak voltage detector 100, the peak-to-peak voltage detector 200 is much more complicated, requiring an input buffer amplifier 210, two separate peak detectors 220 and 230, and a summing block 240. On an integrated circuit, this complexity requires a substantial amount of chip area. Further, the circuit is not particularly well suited to applications targeted to low power consumption, since its large number of active components tends to result in relatively high power consumption.